Trenched isolation regions (such as, for example, shallow trench isolation regions) are commonly utilized in integrated circuitry for electrically isolating electrical components from one another. The isolation regions extend into a semiconductor substrate, and comprise insulative material formed within trenches that have been etched into the substrate.
High density plasma (HDP) oxide has been widely used in trenched isolation regions. A problem that can occur during formation of trenched isolation regions is that voids can become trapped in the trenches during deposition of the insulative material within the trenches. The voids will have dielectric properties different than that of the insulative material, and accordingly will alter the insulative properties of the isolation regions. The voids can also cause issues with further processing steps if the voids are exposed at any time during the processing steps. In response to these problems, numerous technologies have been developed for eliminating void formation within trenched isolation regions.
It is becoming increasingly difficult to eliminate void formation with increasing levels of integration (in other words, with the continuous shrinking of feature sizes with each new generation). Specifically, trenched isolation regions are becoming narrower and deeper with each device generation, which renders it more difficult to uniformly fill the trenched isolation regions with insulative material.
In light of the above-discussed difficulties, it would be desirable to develop new methods for fabrication of trenched isolation regions which alleviate problems associated with voids. Although the invention described herein was motivated, at least in part, by the desire to alleviate problems associated with void formation in trenched isolation regions, persons of ordinary skill in the art will understand upon reading this disclosure and the claims that follow that aspects of the invention can have applications beyond trenched isolation regions.